1. Field of the Invention
The present invention relates to a driving method and a driving circuit of a plasma display panel (PDP).
Development of a PDP having a large screen and a high resolution is proceeding. When the number of cells constituting a screen increases, a misdischarge can be generated easily. In an AC type PDP, equalization of charge of all cells is performed before addressing for forming a charge distribution corresponding to display data, and quality of the equalization affects success or failure of the addressing. Therefore, a driving method that enables high accuracy equalization in a short time is desired.
2. Description of the prior art
AC type PDP utilizes a memory function of a dielectric layer that covers display electrodes. Namely, addressing is performed for controlling charge quantity of a cell in accordance with display data before applying a sustaining voltage Vs having alternating polarity to a pair of display electrodes. The sustaining voltage Vs satisfies the following inequality.
Vfxe2x88x92Vw less than Vs less than Vf 
Here, Vf denotes a discharge starting voltage, and Vw denotes a wall voltage between electrodes. The application of the sustaining voltage Vs causes a display discharge only in cells having wall charge when a cell voltage (an effective voltage of the voltage applied to the electrode plus the wall voltage) exceeds the discharge starting voltage Vf. A light emission caused by a display discharge is referred to as xe2x80x9clightingxe2x80x9d. When shortening the application period of the sustaining voltage Vs, the light emission looks continuous.
Since a cell of a PDP is a binary light emission element, a half tone is reproduced by setting the number of discharges in one frame for each cell in accordance with a gradation level. A color display is a type of the gradation display, and a display color is determined by a combination of luminance values of three primary colors. A gradation display utilizes a method of constituting one frame of plural subframes weight by the luminance and setting the total number of discharges by combining lighting and non-lighting of each subframe. Furthermore, in the case of an interlace display, each of plural fields of a frame is made of plural subfields, and lighting control is performed by a unit of subfield. However, a content of the lighting control is the same as that of a progressive display.
A reset period (addressing preparation period) for initialization of equalizing an electrification state of the entire screen before the addressing is assigned to a subframe along with an address period for addressing and a display period (also referred to as a sustain period) for generating display discharges the number of times corresponding the weight of the luminance. At the end of the display period, there are cells having relatively much remaining wall charge and cells having little remaining wall charge. Therefore, initialization is performed as a preparation process for increasing reliability of addressing.
U.S. Pat. No. 5,745,086 discloses an initialization step in which a first and a second ramp voltages are applied to cells successively. The application of the ramp voltage having a mild gradient prevents drop of contrast by reducing light emission quantity in the initialization and enables setting the wall voltage to any desired value despite of a variation of the cell structure, due to the microdischarge property that will be explained below.
When applying a ramp voltage having increasing amplitude to a cell having an appropriate quantity of wall charge, plural microdischarge are generated during the applied ramp voltage increases under the condition of the mild gradient of the ramp voltage. If the gradient is further reduced, the discharge intensity is decreased, and the discharge period is shortened to become a continuous discharge form. In the following explanation, a periodic discharge and a continuous discharge are generally referred to as a xe2x80x9cmicrodischargexe2x80x9d. In a microdischarge, a wall voltage can be set only by a peak voltage of a ramp waveform. It is because that the generation of the microdischarge keeps the cell voltage to a vicinity of the voltage Vt even if a cell voltage Vc (i.e., a wall voltage Vw plus an applied voltage Vi) that is applied to a discharge space exceeds a discharge starting threshold level (hereinafter denoted by Vt) due to the increase of the ramp voltage. The microdischarge drops the wall voltage to an extent corresponding to the increase of the ramp voltage. The final value of the ramp voltage is denoted by Vr, and the wall voltage at the time point of the final value Vr of the ramp voltage is denoted by Vw. Then, since the cell voltage Vc is maintained at Vt, the following relationship holds.
Vc=Vr+Vw=Vt 
Therefore,
Vw=xe2x88x92(Vrxe2x88x92Vt) 
Since Vt is a constant value determined by electric characteristics of a cell, the wall voltage can be set to any desired vale by setting the final value Vr of the ramp voltage. More specifically, even if there is a minute difference of Vt between cells, the relative difference between Vt and Vw can be equalized for all cells.
In the initialization that generates the microdischarge, the application of the first ramp voltage causes forming of an appropriate quantity of wall charge between the display electrodes. After that, the second ramp voltage is applied so that the wall voltage between the display electrodes approaches the desired value. For example, in the initialization for writing format of addressing, the wall charge is eliminated so that the wall voltage becomes zero. The amplitude of the first ramp voltage is set so that a microdischarge is always generated by the second ramp voltage.
Conventionally, a constant current circuit having a combination of a field effect transistor (FET) and a resister is used as means for applying a ramp voltage. For example, a ramp voltage of positive polarity is applied by connecting the drain of the FET to a display electrode of a cell, and the source of the FET is connected to a power source via the resistor. The gate of the FET is biased to a predetermined potential so as to turn on the FET. Then, a current flows from the power source to the display electrode. The current is limited by the resister, and a predetermined current is supplied to the cell. A cell without a discharge is a capacitive load to a power source. Therefore, the supply of the predetermined current increases the applied voltage between the display electrodes at substantially a constant rate.
Furthermore, instead of a ramp voltage, an obtuse waveform voltage having amplitude increasing exponentially can be applied for generating a microdischarge. However, in an obtuse waveform, the increasing rate of the voltage in the latter portion is so small that the time until the amplitude reaches a predetermined value becomes long. If the increasing rate of the voltage in the latter portion is increased for shortening an application time, the increasing rate of the voltage in the front portion becomes so large that a pulse discharge in which the wall charge changes rapidly can be generated easily instead of the microdischarge. Application of a ramp voltage can shorten the reset period compared with application of an obtuse waveform voltage.
FIG. 16 is a diagram showing a transition of a driving voltage in the conventional method.
Before a microdischarge is generated, a capacitance between the display electrodes is charged by a whole current supplied from the constant current circuit. When a microdischarge starts, a part of the supplied current becomes a discharge current, so that the current for charging the capacitance between the display electrodes decreases. Therefore, the increasing rate of the applied voltage between the display electrodes, i.e., the gradient of the ramp waveform is not constant but alters depending on whether discharge exists or not. In the initialization as a preparation of addressing in a certain subframe, the gradient of the ramp waveform alters from xcex94p11 to xcex94p12 that is smaller than xcex94p11 as a discharge starts if all cells were not lighted in the previous subframe. In this case, since there is little wall charge in the cell when the initialization starts, a discharge starts at the time point when the applied voltage approaches the final value Vr. Therefore, the time Tp1 until the applied voltage reaches the final value Vr is relatively short. In contrast, if all cells were lighted in the previous subframe, a discharge starts when the applied voltage is still low since the cell has a remaining wall charge at the time point of starting the initialization. Therefore, the time Tp2 until the applied voltage reaches the final value Vr is relatively long. The pulse width (application period) Tpr of the applied voltage pulse is set in accordance with the time Tp2. In the conventional method, since the gradient of the ramp waveform alters substantially due to a discharge, the pulse width Tpr cannot be shortened so that a long time is necessary for the initialization. The reset period is preferably as short as possible for securing a time that can be assigned to addressing or sustaining.
Moreover, if a few cells were lighted in the previous subframe, a discharge starts in a few cells when the applied voltage is still low. The gradient of the ramp waveform alters from xcex94p11 to xcex94p13 that is smaller than xcex94p11. After that, when the applied voltage approaches the final value Vr, a discharge starts in the remaining many cells, and the gradient of the ramp waveform alters from xcex94p13 to xcex94p12xe2x80x2that is smaller than xcex94p13. In this case, when a discharge occurs in a few cells, an excessive current is supplied so that a pulse discharge occurs easily instead of a microdischarge. A current is distributed when a discharge occurs in many cells simultaneously. In this case, however, the current is concentrated in a few cells. In order to prevent the pulse discharge, the gradient xcex94p11 of the ramp waveform at non-discharge is required to be sufficiently small. However, if the gradient xcex94p11 is decreased, the pulse width Tpr is elongated.
An object of the present invention is to reduce a rate of increase of the voltage so as to shorten a reset period. Another object is to prevent an excessive discharge in the reset period so that a reliability of initialization is increased.
According to the present invention, a capacitance element is connected in parallel with a cell in a bias period for applying an increasing voltage within the reset period, and a current is supplied from a constant current circuit to the capacitance element and the cell. When a discharge is generated in a cell, a current of charging an interelectrode capacitance of the cell and the capacitance element decreases by the quantity of the discharge current. The decreasing quantity is distributed to the cell and the capacitance element. Therefore, the decreasing quantity of the current charging the interelectrode capacitance is less than that in the case where no capacitance element is connected. Namely, a rate of increase of the applied voltage becomes small so that the time until the applied voltage reaches the final value is shortened.
In addition, according to the present invention, the supply of a current from the constant current circuit to the cell in the reset period is performed intermittently in accordance with a quantity of a display load in the display period. Because of the intermittent supply of the current, the applied voltage waveform becomes a step waveform. The intermittent supply in accordance with a display load can enlarge an increasing rate of the voltage as much as possible when a discharge is generated in many cells. Thus, the time necessary for initialization can be shortened, and an excessive discharge can be avoided when a discharge is generated in a few cells.